Please use this identifier to cite or link to this item: https://doi.org/10.1109/TCAD.2021.3132551
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dc.titleHiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction
dc.contributor.authorDhananjaya Wijerathne
dc.contributor.authorZhaoying Li
dc.contributor.authorANUJ PATHANIA
dc.contributor.authorTULIKA MITRA
dc.contributor.authorLothar Thiele
dc.date.accessioned2022-01-06T07:52:44Z
dc.date.available2022-01-06T07:52:44Z
dc.date.issued2021-02-05
dc.identifier.citationDhananjaya Wijerathne, Zhaoying Li, ANUJ PATHANIA, TULIKA MITRA, Lothar Thiele (2021-02-05). HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems : 1192-1197. ScholarBank@NUS Repository. https://doi.org/10.1109/TCAD.2021.3132551
dc.identifier.issn0278-0070
dc.identifier.issn1937-4151
dc.identifier.urihttps://scholarbank.nus.edu.sg/handle/10635/213156
dc.description.abstractCoarse-Grained Reconfigurable Array (CGRA) has emerged as a promising hardware accelerator due to the excellent balance between reconfigurability, performance, and energy efficiency. The performance of a CGRA strongly depends on the existence of a high-quality compiler to map the application kernels on the architecture. Unfortunately, the state-of-the-art compiler technology falls short in generating high-performance mapping within an acceptable compilation time, especially with increasing CGRA size. We propose HiMap – a fast and scalable CGRA mapping approach – that is also adept at producing close-to-optimal solutions for regular computational kernels prevalent in existing and emerging application domains. The key strategy behind HiMap’s efficiency and scalability is to exploit the regularity in the computation by employing a virtual systolic array as an intermediate abstraction layer in a hierarchical mapping. HiMap first maps the loop iterations of the kernel onto a virtual systolic array and then distills out the unique patterns in the mapping. These unique patterns are subsequently mapped onto sub-spaces of the physical CGRA. They are arranged together according to the systolic array mapping to create a complete mapping of the kernel. Experimental results confirm that HiMap can generate application mappings that hit the performance envelope of the CGRA. HiMap offers 17.3x and 5x improvement in performance and energy efficiency of the mappings compared to the state-of-the-art. The compilation time of HiMap for near-optimal mappings is less than 15 minutes for 64x64 CGRA, while existing approaches take days to generate inferior mappings.
dc.description.urihttps://ieeexplore-ieee-org.libproxy1.nus.edu.sg/document/9473916
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.typeConference Paper
dc.contributor.departmentDEPT OF COMPUTER SCIENCE
dc.description.doi10.1109/TCAD.2021.3132551
dc.description.sourcetitleIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
dc.description.page1192-1197
dc.published.statePublished
dc.grant.fundingagencySingapore Ministry of Education Academic Research Fund TI 251RES1905
dc.grant.fundingagencyHuawei International Pte. Ltd
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