Subthreshold quasi-delay-insensitive circuit designs

Abstract

With increasing operating speed, circuit complexity and decreasing feature size of digital circuits, it becomes difficult to design traditional synchronous circuits due to clock skew and jitter in clock distribution. In addition, large power is consumed by clock tree itself. Asynchronous circuits that synchronize the data communication with local handshake signals are believed to be one of candidates that is suitable for large systems. Quasi-delay-insensitive (QDI) circuit is a member of asynchronous family. Its functionality is independent of the delays between different components in the circuit. Therefore it has better robustness against delay variation caused by Process, Voltage and Temperature (PVT) variations than synchronous circuits. As we know, this delay variation may fail synchronous design¿s timing assumption. Otherwise large timing margin must be built into the design to guarantee the functionality of synchronous circuits in all conditions. However, this degrades the synchronous circuit¿s performance greatly. On the other hand, QDI circuits are able to run as fast as the physical environment allows. The effect of PVT variation is more significant in subthreshold region where delay changes dramatically along with it. Operating circuits in subthreshold region is beneficial in terms of ultra-low power consumption and energy efficiency. Therefore operating QDI circuits in subthreshold region, on one hand, reduces power consumption; on the other hand, suppresses the susceptibility to PVT variations. In this thesis, we study the subthreshold QDI circuit design for both combinational and sequential logic circuits. We first show, by mean of examples, that subthreshold QDI full adder exhibits quite competitive Power-Delay Product (PDP). Then we move on to explore the design of a QDI FIR filter. Finally, complete system, i.e. filter bank for Electrocardiograph (ECG) sensors in Body Sensor Networks, will be demonstrated.