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|Title:||Design and implementation of ultra-low-power sensor interface circuits for ECG acquisition||Authors:||XU XIAOYUAN||Keywords:||ECG, Ultra-low-power, Sensor Interface, Biosignal Acquisition, Integrated Circuit Design, Subthreshold Mixed-signal IC||Issue Date:||26-Mar-2010||Citation:||XU XIAOYUAN (2010-03-26). Design and implementation of ultra-low-power sensor interface circuits for ECG acquisition. ScholarBank@NUS Repository.||Abstract:||This work is about the design and implementation of ultra-low-power biomedical sensor interface circuits that are suitable for telemetric medical applications and in particular for wearable ECG devices. It is motivated by the increasing awareness and demand in pervasive and remote personal healthcare services due to population ageing; inspired and impelled by the rich options offered by today¿s microelectronic technology and material and biomedical sciences. Its preliminary outcome, as documented in the dissertation, is the world¿s first sub-uW ECG sensor interface chip. The sensor interface chip integrates a low-noise frontend amplifier with programmable bandwidth and gain, and a 12-bit SAR ADC incorporating a dual-mode low-power clock module. The ultra-low power consumption is achieved through optimal system partitioning derived from the most efficient S/H duty ratio, and extensive applications of subthreshold circuit design techniques. A novel cross-coupled pseudo-resistor structure that favors both electrical balance and resistance tunability is proposed for onchip high-pass cutoff frequency tuning. The gain control is implemented by a novel ¿flip-over-capacitor¿ structure that eliminates the low frequency gain interruption due to the finite off-state resistance of the MOS switches. The dual-mode clock module offers options of both a more accurate crystal driver and a more power conserving relaxation oscillator, targeting applications with different power and accuracy requirements. Fabricated in AMS 0.35-um CMOS baseline process and operated at 1-V supply, the sensor interface chip features 0.6% of worst-case THD, 57 dB of dynamic range and 3.26 of NEF for the frontend amplifier; +0.8/-0.6 LSB of DNL, ±1.4 LSB of INL and 10.2 ENOB for the ADC. The power consumption for the entire chip is measured to be 445 nW in the minimum band QRS detection mode, and 895 nW in the full band ECG acquisition mode. A miniature ECG plaster prototype based on the sensor interface chip and a commercial ZigBee transceiver is thereafter demonstrated. The captured ECG data are either stored locally to a Micro SD card or sent out to base stations or routers over ZigBee radio. Also documented in the dissertation are some supportive information, considerations and analyses throughout the work. They include the introduction to the cardiac cycle, ECG signals and lead systems; the studies on the settling behavior and scalability of the first order S/H system, and on the static nonlinearity of the binary search capacitive DAC, etc.||URI:||http://scholarbank.nus.edu.sg/handle/10635/20424|
|Appears in Collections:||Master's Theses (Open)|
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