LOW-POWER HARDWARE SECURITY PRIMITIVES IMMERSED IN LOGIC AND MEMORY

Abstract

Security of ubiquitous connected systems (e.g., IoT nodes) has gained more importance due to the growing cost of security breaches. The security of these devices can be easily compromised with malicious physical access due to in-field operation and the recent affordability of physical attacks. Design of the secure system on chip (SoC) requires energy- and cost-efficient hardware security primitives (e.g., PUF, TRNG, cryptographic cores) to implement root-of-trust. Different design challenges are low energy efficiency, design margining, robust operation and design methodology. Firstly, a fully-synthesizable PUF is proposed in 40 nm featured 3.2% BER with low design effort and in-logic obfuscation. Design margining is eliminated with the proposed PUF-based key generation architecture featuring run-time adaptation with 2X high energy efficiency in 40 nm. Also, a novel unified all-digital and fully-synthesizable architecture for TRNG and cryptographic core is reported with the highest area efficiency in 40 nm. Further, a unified in-memory TRNG and multi-bit PUF is proposed using 16 kb SRAM in 28 nm by reusing memories. Lastly, a security scalable cryptographic core is implemented in 40 nm with dynamic key length from up to 256-bit.