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Title: Design and characterization of interposers for high speed fine pitch wafer level packaged device testing
Keywords: Interposer, Fine-Pitch, High-Speed, Vertical-Compliance, Wafer-Level-Test, Characterization
Issue Date: 20-Jan-2006
Citation: TAN PANG HOAW, JIMMY (2006-01-20). Design and characterization of interposers for high speed fine pitch wafer level packaged device testing. ScholarBank@NUS Repository.
Abstract: Interposer serves as electromechanical interface between test signal generator and the device under test. The objective of this work is to design interposer for the application of fine-pitch, high-speed wafer-level packaged device testing. It is to achieve reliable test results at the speed of 5 GHz, with fine pitch (100 micrometers) and pin count of thousands. Another important test requirement is to provide vertical compliance for the wafer level interconnects. Two designs were studied. The first interposer is a MEMS based interposer and the second one is an elastomer based interposer. The thesis, with detailed methodologies of design, electrical modeling and characterization, describes how these interposers can achieve the test specifications. A prototype for the elastomer interposer was fabricated and functionally tested. Measurements of the test were compared to the simulations. Optimizations and parametric variations studies on the high speed performances of these interposers were examined.
Appears in Collections:Master's Theses (Open)

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