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Title: Model-driven timing analysis of embedded software
Authors: JU LEI
Keywords: Embedded system design, Model based design, Timing analysis, WCET analysis, Schedulability analysis, Synchronous language
Issue Date: 6-Jun-2010
Citation: JU LEI (2010-06-06). Model-driven timing analysis of embedded software. ScholarBank@NUS Repository.
Abstract: In recent years, model-based design has become an industrial standard to address problems associated with designing complex embedded software. For hard real-time system domains including avionics and automobiles, static timing analysis is of paramount importance. To reinforce the advantages of model-based design approach, timing analysis must be seamlessly coupled to provide designers with temporal behavior of the system at early design stages. In this thesis, we study various models (applicable at different design levels) and corresponding timing analysis techniques. We show that to achieve correct and accurate timing estimates in model-driven embedded software design, both model-level and micro-architectural information need to be considered in the timing analysis. Code-level WCET analysis determines worst-case timing behavior of a program on a micro-architecture for all possible inputs. In a model-based design framework, executable code is automatically generated from a high-level model. We show that accurate code-level timing estimates can be achieved by taking into account the high-level information in the timing analysis. We discuss our model-driven WCET analysis in the context of Esterel, a representative synchronous programming model. Our proposed timing analysis utilizes model-level information to help determining program path and context in the WCET analysis of generated C code from Esterel specification. In addition to strengthening existing WCET analysis approaches for sequential programs with our model-driven techniques, we also propose a framework for timing analysis of multiprocessor execution of Esterel specifications. Experimental results show that our analysis substantially reduces WCET over-estimation. In system-level schedulability analysis, WCET of each individual task is provided as input parameters, which captures the worst-case intra-task timing behavior for the task. Traditional task graph-based system models and their schedulability analysis essentially concern with independent tasks and single-processor execution. We propose schedulability analysis for standard Message Sequence Chart (MSC) based system models, which are widely used for describing interaction scenarios between the components of a distributed system. We also capture the timing effects of the shared bus for intertask communication in our proposed analysis. We illustrate the details of our analysis using a setup from the automotive electronics domain, which consist of two real-life application programs (that are naturally modeled using MSCs) running on a platform consisting of multiple electronic control units (ECUs) connected via a FlexRay bus.
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