Please use this identifier to cite or link to this item: https://doi.org/10.1109/TVLSI.2019.2950959
Title: Automated Design of Reconfigurable Microarchitectures for Accelerators under Wide Voltage Scaling
Authors: SAURABH JAIN 
LIN LONGYANG 
ALIOTO,MASSIMO BRUNO 
Keywords: Energy consumption, VLSI, minimum-energy point, wide voltage-frequency scaling, CAD algorithms, pipelining
Issue Date: 15-Nov-2019
Publisher: IEEE
Citation: SAURABH JAIN, LIN LONGYANG, ALIOTO,MASSIMO BRUNO (2019-11-15). Automated Design of Reconfigurable Microarchitectures for Accelerators under Wide Voltage Scaling. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (3) : 777-790. ScholarBank@NUS Repository. https://doi.org/10.1109/TVLSI.2019.2950959
Rights: Attribution-NonCommercial-NoDerivatives 4.0 International
Series/Report no.: IEEE Trans. on VLSI Systems;vol. 28, no. 3
Abstract: This paper introduces a systematic methodology to design microarchitectures that are reconfigurable down to the pipeline stage. Reconfigurable microarchitectures were showed to provide significant energy improvements in accelerators under wide voltage scaling. However, prior art is based on ad hoc techniques that limit their applicability, without addressing the challenge of enabling general design flows for reconfigurable microarchitectures. The proposed methodology introduces the unprecedented capability of translating a conventional fixed microarchitecture into a reconfigurable one. The methodology relies on commercial EDA tools, which are integrated into a design flow through the manipulation of the gate-level netlist via a set of graph algorithms. The proposed methodology is shown to be architecture-agnostic, fully automated and applicable to designs that are either developed at the RTL level, or provided by third-party soft IP vendors. Ultimately, the proposed methodology allows to add microarchitectural adjustment as a run-time knob to augment the energy benefits of wide voltage scaling. Reconfiguration is shown to improve the energy efficiency by up to 35% beyond conventional DVFS, through the analysis of various test vehicles.
Source Title: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
URI: https://scholarbank.nus.edu.sg/handle/10635/183443
ISSN: 10638210
DOI: 10.1109/TVLSI.2019.2950959
Rights: Attribution-NonCommercial-NoDerivatives 4.0 International
Appears in Collections:Staff Publications
Elements

Show full item record
Files in This Item:
File Description SizeFormatAccess SettingsVersion 
remicro_tvlsi.pdf2.48 MBAdobe PDF

OPEN

Post-printView/Download

SCOPUSTM   
Citations

1
checked on May 12, 2021

Page view(s)

52
checked on Apr 29, 2021

Download(s)

2
checked on Apr 29, 2021

Google ScholarTM

Check

Altmetric


This item is licensed under a Creative Commons License Creative Commons