SINGLE PHASE POWER FACTOR CORRECTION: INVESTIGATION AND DEVELOPMENT OF ADVANCED TECHNIQUES

Abstract

To improve the quality of utility power supply, regulatory bodies have begun to impose strict harmonic-standards for the input current drawn by ac-to-dc power electronic equipment connected to the utility. Power Factor Correction (PFC) circuits are therefore becoming necessary to meet the requirements in the standards. The main objective of the present research is to investigate and develop new high-performance active PFC techniques for single-phase applications. The focus has mainly been in achieving high efficiency, low part count, reduced size, weight and cost. The report first presents a comprehensive review and classification of developments in single-phase PFC area. Both passive and active PFC techniques are covered in the review. Appropriate classification criteria are used to accommodate past and future developments within a general framework. Based on the dynamic performance of output dc voltage, the active PFC techniques are broadly classified into 1) PFC techniques with slow output dynamics, and 2) PFC techniques with fast output dynamics. The PFC techniques with slow output dynamics typically require a further downstream dc-to-dc converter to meet the load requirement, whereas those with fast output dynamics can cater to load requirements directly. The present work has made contributions in both of these areas. In the area of PFC with slow output dynamics, a half-bridge boost topology and its dual buck circuit, were both investigated for use as front-end PFC converters. These were studied owing to their lower total semiconductor ‘on-voltage’ drop which leads to high efficiency. The causes for the observed imbalances in the dc-link capacitor voltages (boost circuit) and in dc-link inductor currents (dual buck circuit) were studied using appropriate circuit and mathematical models. Control methods to overcome the imbalances in both the cases are established. Averaged circuit model, which can be used for steady-state analysis and also for fast and efficient simulation, have been developed for both cases. The results of the analyses were verified through simulation (both switched and averaged circuit models) and also through experimental work. Equations and plots useful to a design engineer, have also been developed for both the cases. In the area of PFC with fast output dynamics, three new PFC techniques were proposed. Among these, the input current in the Input-Shunt PFC (ISPFC) and the Partially-Parallel PFC (P2PFC) techniques are sinusoidal with power factor close to unity, whereas in the case of Fully-Parallel PFC (FPPFC) technique it is non-sinusoidal. The main thrust in these PFC techniques is the reduced overall processed-power compared to the cascaded technique. Hence, these techniques aim to offer (without sacrificing the dynamic performance) advantages such as (i) improved efficiency and (ii) reduced cost, size and weight. The schemes, when implemented using specific converters, were analysed in detail and the results were verified against switched and averaged model simulation results. In the case of ISPFC technique, experimental verification is also presented. The report concluded with identification of future work that can be carried out in each of the topics investigated.