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Title: Development and characterization of high-k dielectric/germanium gate stack
Keywords: semiconductor, germanium, MOS, transistor, high-k, passivation,
Issue Date: 7-Dec-2009
Citation: XIE RUILONG (2009-12-07). Development and characterization of high-k dielectric/germanium gate stack. ScholarBank@NUS Repository.
Abstract: Scaling of the gate stack has been a key to enhancing the performance of metal-oxide semiconductor field-effect transistors (MOSFET) in the past 40 years. However, as the MOSFET continues to scale down to tens of nanometers, Si/SiO2 based device is approaching its fundamental limits. The motivation for alternative gate stacks has increased considerably. High-k/Ge gate stack is very promising for future nanoscale devices because it improves the device performance in terms of both drive current and power consumption. The most important technical issue for high-k/Ge MOSFET technology is the passivation of the Ge surface. In this study, two approaches to improve the high-k/Ge interface qualities were investigated. The first approach was using pre-gate surface passivation. Two pre-gate surface passivation techniques were investigated. They are sulfur passivation and silicon nitride passivation. By suppressing the Ge diffusion into high-k dielectrics using those surface passivation techniques, improved high-k/Ge gate stack quality has been achieved. The second approach to improve the high-k/Ge interface quality is to adopt proper post-gate treatment processes. For the first time, we proposed and demonstrated a post-gate CF4 plasma treatment process to incorporate fluorine (F) into high-k/Ge gate stacks. Interface quality and high-k bulk quality were significantly improved by F incorporation. The post-gate treatment was also found to be compatible with pre-gate surface passivation. By applying both techniques on high-k/Ge gate stack, the optimum interface quality was able to be achieved. Variable rise/fall time charge pumping method was also used to characterize the interface properties of Ge MOSFETs. We found that F passivation was capable to reduce interface traps that located in the both bottom half and upper half of the Ge bandgap. Asymmetric Dit distribution in Si passivated Ge MOSFETs was also observed by using this technique, which can be the possible cause of severe electron mobility degradation for Ge nMOSFETs.
Appears in Collections:Ph.D Theses (Open)

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