DSP AND FPGA IMPLEMENTATION OF ACOUSTIC ECHO CANCELLING

Abstract

Acoustic echo cancellation using various adaptive algorithms has been suggested by many researchers. A particularly interesting approach uses a new implementation of the LMS-Newton algorithm. It is reported that software simulations show good results of this implementation in a teleconferencing set-up. Based on this new implementation of the LMS-Newton algorithm, software simulations and real-time implementation of acoustic echo cancellation in a teleconferencing-like environment using a DSP card is first presented. The results show that the new implementation offers better echo cancellation performance as compared to the Normalised LMS (NLMS) algorithm. An alternative realization of the LMSNewton algorithm with a Field Programmable Gate Array (FPGA) is also presented. A 578- tap adaptive filter is fitted into one Xilinx XC4062XL FPGA, which operates at a sampling rate of up to 29.4 kHz. This FPGA implementation outperforms by a wide margin the DSP implementation, which uses the state-of-the-art Analog Devices ADSP-21062 DSP. The FPGA design can be cascaded to realize long length AECs (at multiples of 578 taps) with no degradation in sampling speed and without the need for any glue logic. An interesting finding which has been ignored in most of the earlier publications is that although a relatively long word length should be used for the filter tap weights to prevent the stalling phenomenon, the number of actual tap-weight bits which should be used to calculate the filter output can be much less. A prototype board is built around the Xilinx XC4062XL FPGA to confirm the proposed design in an actual teleconferencing environment. The completed board is a full acoustic echo canceling system that has on board the FPGA, an Analog Devices AD7862 ADC, an Analog Devices AD7245 DAC and a clock source provided by the HARRIS 82C84A CMOS clock generator driver. No external control circuitry is needed. Good acoustic echo canceling performance has been observed.