MMIC LNA DESIGN AND GAAS FET MODELING : DC, SMALL-SIGNAL, AND NOISE

Abstract

In this thesis, a complete grasp of Microwave Monolithic Integrated Circuits (MMIC) low noise amplifier (LNA) development has been carried out. Firstly, an MMIC LNA employing GaAs MESFET has been successfully built right for the first time with the introduction of a new design methodology: study and optimize FET performance and its gate structure (fingers and unit gate width) during design phase. Secondly, after studying of the existing modeling approaches, a new indirect FET de modeling method is proposed and performed, in which the current is derived through drain-port power and conductance models. It has been shown that the new method has more flexibility in choosing model functions than conventional ones. Thirdly, for statistical modeling, the influence of process variation and temperature dependence on FET small-signal model equivalent elements has been studied from FETs fabricated in different wafer lots and measured at different temperatures. Fourthly, on-wafer noise source-pull measurement has been done and it shows that the PET with the same gate width has different dependence on bias, if the FET gate structure is different. Fifthly, a parameter-extraction method linked with a FET noise model is shown to give a lower sensitivity of Fmin, Rn, ?foptl, and ?f'opt to individual data than conventional approaches where Fmin, Rn, ?foptl, and ?f'opt are directly extracted from source-pull data. Lastly, the source impedance pattern for noise source-pull measurement has been analyzed through a perturbation method. It is shown through statistical simulation that a pattern developed with this method gives lower extraction-sensitivity to measurement error than some other state-of-the-art patterns