DSP-BASED RAPID PROTOTYPING PLATFORM FOR CONTROLLER DESIGN

Abstract

Until recently, PC-based motion control was not popular in the Numerical Control (NC) industry. This was due to the inherent limitations of the Personal Computer (PC) architecture, bus speed as well as the lack of floating point computational power required. By proposing an ideal model Industry Standard Architecture (ISA) Digital Signal Processor-based (DSP) motion controller card based on a superset of specifications of existing motion controller cards, the inherent limitations of the PC architecture can be overcome. This ideal model aims to overcome the low ISA bus data transfer rates and other inherent limitations by performing all motion and floating point computations on the card itself. The PC complements the ideal model by providing a convenient platform for monitoring the low bandwidth signals. The ideal model ISA DSP-based motion controller is designed for an 8-axis robot. The computational core is based on the TMS320C30, a 32-bit floating point DSP. This core is supported by 1Mx32 bit zero-wait state RAM, giving up to 4M words of storage. To support the computational core in a real-time environment, a multi-level interrupt system was utilised. The ideal model provides up to 32 multiplexed 16-bit channels via 4 independent 16- bit A/D channels and 8 synchronous updating 16 bit D/A channels. The analog inputs are designed with software programmable input gains and software programmable anti-aliasing filter bandwidths. For interfacing with industry standard optical encoders, the ideal model also features an octal optical encoder decoder. To interface with motor drivers, an octal pulse width modulator (PWM) unit was provided. For general purpose input/output (I/O), the model is designed to accept 64 digital inputs and provide 32 digital outputs As most of the hardware components in the ideal model are currently available as integrated circuits, analog cores or digital cores, the work described in this thesis focuses on implementing and testing the proposed system architecture and developing glue logic and proprietary designs in Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) to supplement the existing hardware. These VHDL designs are essential for System-On-Chip (SOC) integration on Application Specific Integrated Circuits (ASIC). This methodology is in line with the current SOC design revolution which completely encompasses the semiconductor, Electronic Design Automation (EDA), as well as the computer and embedded system industries. A set of reusable VHDL designs for an ISA DSP-based PC Controller Card has been developed. This set of VHDL designs encompasses Bus Control Interface [1], Octal Optical Encoder Decoder [2], Octal Pulse Width Modulation (PWM) generator, and a multi-level programmable interrupt control (PIC). To establish that the proposed system architecture is sound and feasible, several prototype modules of the ideal model ISA DSP-Based PC Controller Card were developed systematically. These prototypes include digital Input/Ouput (I/O) display, linear motor driver, motor with built-in optical encoder prototype, 3-chip octal optical encoder decoder, SIMM72 SRAM modules, single RAM bank, single D/A module and Hex D/A module. From the findings of the tests performed on the modules of the proposed system architecture, it is concluded that the system architecture design is feasible. However, due to the constraints of the implementation on double-sided PCB, the work concludes with several recommendations for future enhancements which can only be made possible through the use of multi-layer PCB designs.