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|Title:||Advanced source and drain contact engineering for multiple- gate transistors||Authors:||LEE TEK PO RINUS||Keywords:||Silicide, FinFET, CMOS, Schottky Barrier, NiSi||Issue Date:||18-Aug-2009||Citation:||LEE TEK PO RINUS (2009-08-18). Advanced source and drain contact engineering for multiple- gate transistors. ScholarBank@NUS Repository.||Abstract:||Geometrical scaling is reaching its fundamental limits after four decades of continuous downsizing of device dimensions to increase the cost per function of integrated circuits. As of the writing of this thesis, the 22 nm technology generation is under-going development at leading semiconductor companies. These companies have indicated that multiple gate transistor designs are promising architectures for extending device performances. These transistors offer improved electrostatic control and steeper subthreshold swings compared to planar transistor designs. However, the manufacturability of these transistor designs is still an issue as they suffer from a significant increase in parasitic capacitances and resistances due to its inherent design. In this thesis, a novel metal alloy concept for electron and hole barrier height engineering was developed to address the escalating issue of parasitic source/drain (S/D) series resistances (or external resistance) in nanoscale multiple-gate field-effect-transistors (MuGFETs). Various process integration challenges relating to technology demonstrations for the proposed concept on N- and P-channel MuGFETs were identified and addressed in this thesis. For N-channel MuGFETs (N-MuGFETs), new materials such as ytterbium silicide, nickel aluminide disilicide, and nickel dysprosium silicide:carbon were developed for external resistance (REXT) reduction.||URI:||http://scholarbank.nus.edu.sg/handle/10635/17722|
|Appears in Collections:||Ph.D Theses (Open)|
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