Advanced gate stack for CMOS nanotechnology

Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/17553

DC Field	Value
dc.title	Advanced gate stack for CMOS nanotechnology
dc.contributor.author	LIM EU-JIN ANDY
dc.date.accessioned	2010-07-13T18:00:47Z
dc.date.available	2010-07-13T18:00:47Z
dc.date.issued	2008-12-16
dc.identifier.citation	LIM EU-JIN ANDY (2008-12-16). Advanced gate stack for CMOS nanotechnology. ScholarBank@NUS Repository.
dc.identifier.uri	http://scholarbank.nus.edu.sg/handle/10635/17553
dc.description.abstract	Metal gate/high-k dielectric gate stacks are required for enhanced device performance in sub-45 nm CMOS technology nodes. Full silicidation of a polysilicon gate electrode with nickel is an attractive metal gate option and novel methods were explored to modulate the mid-gap work function (WF) of NiSi gate. Nickel-alloying with either terbium, or aluminum achieved a gate WF lowering of about ~0.2 b
dc.language.iso	en
dc.subject	Metal gate, Gate Stack, Work Function, CMOS
dc.type	Thesis
dc.contributor.department	NUS GRAD SCH FOR INTEGRATIVE SCI & ENGG
dc.contributor.supervisor	YEO YEE CHIA
dc.description.degree	Ph.D
dc.description.degreeconferred	DOCTOR OF PHILOSOPHY
dc.identifier.isiut	NOT_IN_WOS
Appears in Collections:	Ph.D Theses (Open)

File	Description	Size	Format	Access Settings	Version
AndyLim_PhD_Metal Gate Technology_2008_Final.pdf		2.85 MB	Adobe PDF	OPEN	None	View/Download

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