A RECONFIGURABLE PIPELINED PROCESSOR FOR REAL TIME IMAGE PROCESSING

Abstract

The advent of field programmable gate arrays (FPGAs) has provided a new tool in the development of specialized hardware for many real time applications in image processing, vision control, and robotics [ 1-7]. These applications have long depended on application-specific integrated circuits (ASICs) which are hardware intensive and very few support reconfigurability, mainly in designs with general purpose microprocessors. This project aims to produce a feasible design for a Reconfigurable Pipelined Processor (RPIP) using FPGAs to achieve both the processing speed of ASICs and a sufficient degree of flexibility in reconfigurability for a class of image processing algorithms. Each processing element (PE) in this multiprocessor system is based on a single hardware design, and a chain of PEs can be connected to form a pipeline structure. A stream of data, which can be images, voice or video, enters the pipeline and undergoes a set of pre-defined transformations specified by digital signal processing (DSP) algorithms and produce useful information for verification, inspection or immediate display.