Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/174694
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dc.title3D VISUAL INSPECTION OF IC BONDING WIRES
dc.contributor.authorHAN XIAO
dc.date.accessioned2020-09-08T08:51:24Z
dc.date.available2020-09-08T08:51:24Z
dc.date.issued1998
dc.identifier.citationHAN XIAO (1998). 3D VISUAL INSPECTION OF IC BONDING WIRES. ScholarBank@NUS Repository.
dc.identifier.urihttps://scholarbank.nus.edu.sg/handle/10635/174694
dc.description.abstractThis thesis describes a visual inspection system for IC bonding wires. The aim is to detect defects such as lifted, tight and sagging wires, which are related to the 3D wire profiles. The system is based on the application of the stereo vision technique. Using a single-camera setup, stereo views of the IC chip can be obtained by rotating the chip under the camera. After analyzing the imaging geometry of the stereo system, procedures are proposed to calculate necessary system parameters for the reconstruction of 3D depth information. Rectification of the stereo image pair, which is necessary to achieve a simple epipolar geometry, is also discussed. Edges of the wire image are detected and localized with subpixel accuracy. Two different algorithms have been developed to extract the edge features: one is based on the step edge model, the other on the line-edge model. Edges are then linked to form curves, and matching is conducted between the two ordered curve lists of a stereo pair. The matching process is divided into two steps. The first step is to find the local optimum match for each curve; results from local matching are then combined to give the global optimum. Test images are analyzed and the results clearly show the potential of the approach. The estimated resolution of the height measurement is 14 µm, which is about one-fortieth of the maximum height of the wire loops. The processing time for a stereo image pair is of the order of seconds when the host computer is a 300 MHz Pentium II PC. The high speed in solving the stereo matching problem makes this approach well suited for real time implementation with appropriate hardware.
dc.sourceCCK BATCHLOAD 20200918
dc.typeThesis
dc.contributor.departmentELECTRICAL ENGINEERING
dc.contributor.supervisorONG SIM HENG
dc.contributor.supervisorYE QIN ZHONG
dc.description.degreeMaster's
dc.description.degreeconferredMASTER OF ENGINEERING
Appears in Collections:Master's Theses (Restricted)

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