Please use this identifier to cite or link to this item:
https://scholarbank.nus.edu.sg/handle/10635/174671
DC Field | Value | |
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dc.title | MULTIPROCESSOR BASED IMPLEMENTATION OF A VIDEO COMMUNICATION ALGORITHM | |
dc.contributor.author | CHUA KUAN SEAH | |
dc.date.accessioned | 2020-09-08T08:50:42Z | |
dc.date.available | 2020-09-08T08:50:42Z | |
dc.date.issued | 1998 | |
dc.identifier.citation | CHUA KUAN SEAH (1998). MULTIPROCESSOR BASED IMPLEMENTATION OF A VIDEO COMMUNICATION ALGORITHM. ScholarBank@NUS Repository. | |
dc.identifier.uri | https://scholarbank.nus.edu.sg/handle/10635/174671 | |
dc.description.abstract | The Texas Instruments (TI) TMS320C80 Multimedia Video Processor (MVP) is a new generation single chip multiprocessor digital signal processor. It comprises of a single RISC-like floating point based Master Processor (MP) and four integer based Parallel Processors (PPs). All the five processors are fully programmable. The PP has advanced features with a rich set of instructions that support graphics and image processing operations at high speeds. The TMS320C80 MVP provides a powerful platform for developing real-time image and video based applications. This thesis describes the issues and techniques in the implementation of the ITU-T H263 video coding algorithm on the TMS320C80 MVP. The H.263 video coding algorithm is analysed to identify computationally intensive routines that consume many clock cycles so that they may be implemented using low level assembly language instructions. This offers the possibility of executing multiple instructions in parallel. The TMS320C80 MVP is a multiprocessor that is capable of executing a different algorithm on each PP in parallel. The different functional modules of the coding algorithm could be partitioned such that they execute concurrently on the various PPs which are used in a multiple-input-multiple-data (MIMD) configuration. As the encoding process is found to take up significantly more time than the decoding process, the three PPS are used for encoding and a single PP is used for decoding, while the MP performs the video capture and display. The various modules of the coding algorithm are partitioned among the various PPs so that they are "loaded" approximately equally. The modules are subsequently started in a pipelined manner with different modules running concurrently among the various PPs. The Software Development Board, a PC/AT plug-in card, is used for all simulation and testing. The implementation of the H.263 is optimised for the TMS320C80 MVP and is capable of achieving up to 20 frames per second. | |
dc.source | CCK BATCHLOAD 20200918 | |
dc.type | Thesis | |
dc.contributor.department | ELECTRICAL ENGINEERING | |
dc.contributor.supervisor | ASHRAF ALI KASSIM | |
dc.contributor.supervisor | SURENDRA RANGANATH | |
dc.description.degree | Master's | |
dc.description.degreeconferred | MASTER OF ENGINEERING | |
Appears in Collections: | Master's Theses (Restricted) |
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