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Title: Addressing performance bottlenecks for top-down engineered nanowire transistors
Authors: JIANG YU
Keywords: Si Nanowire Transistors, SiGe Nanowire Transistors, Top-Down Process, Gate-All-Around, FUSI Gate Nanowire
Issue Date: 30-Jul-2009
Citation: JIANG YU (2009-07-30). Addressing performance bottlenecks for top-down engineered nanowire transistors. ScholarBank@NUS Repository.
Abstract: The continuous advancement has allowed CMOS technology to meet the demands of higher device density, faster clock rate and lower power consumption. However, as the scaling dimensions shrink down to the sub-100 nm regime, immense physical challenges make the use of conventional scaling techniques alone insufficient. Novel one-dimensional (1D) structures such as semiconductor nanowires (NWs) are considered to be promising structures for nanoscale devices and circuits. In this thesis, several approaches have been investigated in order to address the performance bottlenecks and to further enhance the performance of semiconductor nanowire devices. In this work, Ge rich nanowire transistors are demonstrated with metal gate/high-k gate stack. Using the pattern size dependent Ge condensation technique, lateral hetero-structure Ge nanowire transistors are found to have higher drive current compared to the conventional homo-structure planar devices. Lower backscattering ratio is obtained in this Ge rich nanowire structure. In a cost-effective approach for SiGe nanowire integration, the SiGe core/shell nanowire devices are fabricated on bulk Si substrate. Due to the lattice mismatch between SiGe core and Si shell, the SiGe core channel is under compressive stress, which improves the hole mobility due to hole effective mass reduction. With the surface passivation effect of the Si shell, the interface between the channel and dielectric is greatly improved. The parasitic source and drain (S/D) resistances in extremely scaled Gate-All-Around (GAA) nanowire devices can pathologically limit the device drive current performance. Superior drive current was achieved in short gate length GAA nanowire devices by utilizing metallic nanowire contacts. The parasitic S/D extension resistance was reduced significantly by using the ultra-thin Ni silicidation technique. It is necessary to set the transistor threshold voltages correctly for both n and pFETs for nanowire circuit integrations. Dopant segregated FUSI GAA structure was demonstrated with successful dual work function implementation, achieving symmetrical threshold voltages (±0.3V). Good inverter transfer characteristics and relatively low ring oscillator delay are observed.
Appears in Collections:Ph.D Theses (Open)

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