Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/172972
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dc.titleFully-Synthesizable All-Digital Unified Dynamic Entropy Generation, Extraction and Utilization in a Cryptographic Core for Constrained Secure Systems
dc.contributor.authorSACHIN TANEJA
dc.contributor.authorALIOTO,MASSIMO BRUNO
dc.date.accessioned2020-08-18T00:52:38Z
dc.date.available2020-08-18T00:52:38Z
dc.date.issued2020-07-28
dc.identifier.citationSACHIN TANEJA, ALIOTO,MASSIMO BRUNO (2020-07-28). Fully-Synthesizable All-Digital Unified Dynamic Entropy Generation, Extraction and Utilization in a Cryptographic Core for Constrained Secure Systems. IEEE ASSCC 2020. ScholarBank@NUS Repository.
dc.identifier.urihttps://scholarbank.nus.edu.sg/handle/10635/172972
dc.description.abstractThis work introduces a novel class of fully-synthesizable all-digital True Random Number Generators (TRNGs) using the same private-key cryptographic core for raw dynamic entropy generation, its extraction via post-processing, and its utilization as crypto-key for constrained secure systems. Endogenous random bit generation is achieved via clock pulsewidth overstretching in the digital implementation of private-key cryptographic algorithms using pulsed-latch pipelines, leveraging inherent Shannon confusion and diffusion. Demonstration on a 40-nm testchip based on a SIMON cryptographic core shows 64-bit key encryption down to 0.25 pJ/bit at 0.45 V, random number generation with cryptographic-grade entropy at 2.5 pJ/bit across manufacturing lots, dice, voltages and temperature corners. The overall area is kept well below the 1E6 F2 area wall (F = minimum feature size).
dc.sourceElements
dc.typeConference Paper
dc.date.updated2020-08-10T19:15:52Z
dc.contributor.departmentDEPT OF ELECTRICAL & COMPUTER ENGG
dc.description.sourcetitleIEEE ASSCC 2020
dc.description.placeUnited States
dc.published.statePublished
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