DESIGN AND IMPLEMENTATION OF A LOW BIT RATE SPEECH CODING SYSTEM WITH ONE ENCODER AND THREE DECODERS

Abstract

This project aims to study the design of and implement, in real-time, a 4800 bps HCELP (High quality Code Excited Linear Prediction) coder with one encoder and three decoders. The HCELP coder, derived from the DoD (Department of Defense) CELP coder, is a low-complexity 4800 bps speech coding algorithm. The hardware and software design considerations in using the Texas Instruments floating-point TMS320C3 l DSP chip to implement the HCELP coder to perform, in real-time, a single encoding and three decoding operations simultaneously is first studied. The implementation of interactions with the burst mode controller and microprocessor to perform the required functions in a communication system is then investigated. Finally, a simple error performance of the HCELP coder is evaluated to find out the robustness of the HCELP coder under noisy condition.