CONTEXT DEPENDENT REDUCED INSTRUCTION SET COMPUTER (CD-RISC)

Abstract

Context Dependent architecture makes useful information reusable for subsequent executions. The small repertoire of opcodes and tight coupling of RISC instructions has undoubtably made RISC an excellent candidate in demonstrating the context dependency in instruction execution. The Register Families concept makes use of the fixed operand type associated with certain instructions, hence eliminating the need to specifically state the register in subsequent instructions. on the other hand, the Implicit Register Reference takes advantage of the default register number use by the previous instruction, thereby minimising the need to state the register reference if the same register(s) is being referenced. RISC was developed in 1979, with the success of RISC-I by Professor D.A. Patterson in 1981. It has since grown a long way to its present day commercial success in SPARC. The improved performance of RISC may be attributed to the various key features in the architecture. Most RISC instructions are executed over a single instruction cycle. Only the load and store instructions have direct reference to the external memory. The RISC has fixed instruction format. It emphasizes the compiler effort to optimise the code. Another key feature of the RISC architecture is pipelining. A Register window is used in RISC to speed up the execution of procedural calls. These windows comprise registers belonging to each procedure. And are arranged in an overlapping fashion, such that neighbouring procedure have registers on a shared basis. This improves the input/output in parameter passing a great deal. The instruction fetch time in a branch instruction is cut down by a delayed jump technique, used to optimise the code arrangement at the branch instruction. Another clever implementation in RISC is the use of Register Zero, a dummy register used to cater for generalisation of complex instructions to that of the RISC type. A RISC is characterised by two very important preconditions; the large number of registers and the large execution code size, in order that context dependency can be implemented successfully. In implementing the single operand register family, the following register families are identified: Source Data Register Family Destination Data Register Family Address Register Family Action Data Register Family The double operand register families takes a more complex form. Depending on the permutation of the two operands in the execution, different register families can be established. It is established that the life span of a register can be extended to the next instruction. Two schemes were examined in implementing this transition of register reference. The Flip Operation, which merely flips the destination register reference of the previous instruction to become the source register reference of the current instruction. Double Updating updates the destination register reference as well as the source register reference of the next instruction. It was also found that neither the single nor the double operand Context Dependent - Reduced Instruction Set Computer (CD-RISC) can be easily implemented. Instead a hybrid solution was proposed. Using the context dependent schemes, the double operand can be made to look and executed like a single operand model. The second operand would be inherited from the previous instruction. In evaluating the performance of the CD-RISC, well known results from reliable sources were called upon to provide the basis for a comparative analysis. Three benchmarks were selected; ACKERMAN, BENCHMARK-E and PUZZLE. These benchmarks were compiled using the SPARC machine. The assembly sources for the benchmarks were then analysed and modified to incorporate the features of the context dependent RISC. In place of the multiple operand instructions, single operand reference format was adopted. This was the basis for modification. The other operand reference is inherited from the operand reference of the previous instruction. In so doing, additional dummy instructions (e.g. NOP) were introduced when the completely new context (operand references) were assumed. The results showed that ACKERMAN reduced operand occupancy by 57%, Benchmark-E reduced by 69% and even PUZZLE, being example of the worst case, was reduced by 27%. In all three programs, the number of instructions decreased by 12% for ACKERMAN, 18% for Benchmark-E. However there is an increase of 27% for PUZZLE. The results showed that significant savings were made in operand occupancy when the program was moderately structured. The savings in space was translated into extending the addressable memory space ability, to incorporate a larger immediate field. Reducing the instruction size also improved the instruction fetch time as well as cache misses. This was especially important in big programs. With the growing popularity of RISC development, the significance of this context dependent concept will improve RISC performance.