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Title: A novel synchronization scheme for mostly digital UWB impulse radio architecture
Authors: ZHANG QI
Keywords: UWB, Baker Code, Impulse Radio, Synchronization, Low Power, Mostly Digital
Issue Date: 13-Aug-2009
Citation: ZHANG QI (2009-08-13). A novel synchronization scheme for mostly digital UWB impulse radio architecture. ScholarBank@NUS Repository.
Abstract: Ultra wideband has become hot area of research in recent years. It has promising features such as low power and high data rate support which makes it a suitable candidate to be a future short range wireless solution. While UWB can provide short range and extreme high speed data communication, it could also be used in low data rate applications such as biomedical and WPAN. Among all UWB system architectures, impulse radio structure could facilitate low power and low system complexity implementations. The design of traditional IR UWB transceivers has been studied intensively in literature. The continuous trend of downscaling of CMOS technology has lead to the shift of analog regime to digital counterpart. Mostly digital UWB transceivers have been reported in literature and demonstrated promising results in terms of cost and power consumption. However, some challenges still lie in implementing low power architecture. Among them, synchronization remains as a great challenge for UWB receiver design due to the ultra fine sub-nanosecond scale involved in the transmitted UWB pulses. In this work, traditional UWB transceiver synchronization architecture is studied and reviewed. Conclusion is reached upon that traditional synchronization suffers from a trade of between system complexity and receiver performance. As such, a novel digital synchronization scheme together with mostly digital receiver architecture is proposed. The receiver consists of a low noise amplifier, a threshold detector, a pulse capture block and digital signal processing block. Threshold detector performs an early quantization of the received pulse while the novel pulse capture block eliminates the traditional exhaustive search algorithm for synchronization. Transmitted data are Baker-Code modulated and the DSP block in the receiver decodes the received data. The proposed receiver is implemented in standard CMOS 0.35B5m process. Simulation and measurement results have been presented and the simulated overall power consumption of the receiver without the LNA is 1.9mW. The silicon area consumption is only 0.19 mm^2. The low power and small area benefits are well maintained which makes the proposed scheme suitable for low power low data rate applications.
Appears in Collections:Master's Theses (Open)

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