FIXED AND FLOATING POINT PRECISION OPTIMIZED APPROXIMATION ON EMBEDDED AND PARALLEL ARCHITECTURES

Abstract

The recent emergence of approximable programs sparked a general interest in using low-precision number formats to exploit the trade-off between energy and tolerable accuracy. This thesis focuses on the topic of utilizing these number formats on emerging hardware platforms. For embedded platforms, we propose a set of methods for precisely allocating bitwidth to each variable in the program given an accuracy threshold. For customized hardware which is designed to support fixed-point precision for energy-hungry machine learning applications, we propose a method to adaptively allocate bit-level precision according to hardware-design constraints such as budget, memory bandwidth. For GPU architecture, we focus on the usage of half precision and tensor cores in CUDA programs. We propose the solution to efficiently use half precision with other floating point data types and a framework to utilize low-precision tensor cores to run general CUDA programs.