A Design Framework for Reactive and Time-triggered Embedded Systems via the UML-SystemC bridge

Abstract

Embedded systems are increasingly complex due to the large number of internal components and their interactions. This calls for more effective design methods. System level design methodologies have been proposed in this context as the means to cope with complex large scale embedded systems. The aim of this research is to use UML notations to support system level design of systems in which control ow is event-triggered or time-triggered. We use SystemC as an intermediate representation to do design validation. Our main contributions are: The identification of a subset of UML using which the structure, behavior and requirements for a system can be captured. In addition, we identify the neces- sary UML extension mechanisms and the level of abstraction to facilitate the e cient SystemC-based simulation. A translation framework in which the UML model can be used to generate SystemC code automatically. The generated SystemC code has been proven to offer good simulation speed. The first steps towards tool-supported model association in which UML-based test cases and requirements can be validated at the SystemC level and simula- tion traces can be displayed at the UML level. Case studies to con rm the efficacy of our design approach both in event- triggered and time-triggered settings.