Novel III-V mosfet integrated with high-k dielectric and metal gate for future CMOS technology

Abstract

InGaAs is a promising III-V candidature for CMOS application for its high electron mobility. In this work, the fabrication and analysis of novel InGaAs n-MOSFET are carried out. The main processes include material growth, pre-gate cleaning, CVD high-k deposition, gate definition, implantation, dopant activation and contact formation. First study is the CVD high-k directly deposited onto InGaAs. It is found that InGaAs has better integration with high-k comparing to GaAs. Then InGaAs MOSFET is fabricated by the self-aligned method. Secondly, further interface engineering with plasma PH3 passivation is introduced into the MOSFET fabrication. Analysis shows that the chemical composition on the surface after PH3 treatment. It results in improvement of surface quality and helps in the InGaAs integration with high-k dielectric. Transistor performance has significant improvement. Thirdly, a sub 100 nm InGaAs MOSFET is fabricated. Lastly, the limitation of current device and process are discussed.