Advanced source and drain contact engineering for low parasitic series resistance

Abstract

Complementary Metal-Oxide-Semiconductor (CMOS) scaling and the application of strain have led to the increasing dominance of parasitic source/drain (S/D) series resistance. This is expected to limit device performance in the 32 nm technology node and beyond. In this work, novel silicide processes and materials were evaluated as potential solutions to address the parasitic series resistance issue.