Schottky source/drain transistor integrated with high-k and metal gate for sub-tenth nm technology

Abstract

This PhD project attempts to explore the feasibility of integration of germanide Schottky source/drain (S/D) Ge channel MOSFET with high-k gate dielectric and metal gate for sub-tenth nm technology application. Systematic exploration of metal germanide for Ge p- and n-MOS applications have been carried out. Germanium p-MOSFET with Ni- or Pt- germanide Schottky S/D was successfully fabricated on n-Ge-substrate with HfO2/TaN gate stack. Rear earth metal Er or Yb germanide and NiGe with modified electron barrier height were studied for Ge n-MOS application. Moreover, laser annealing was implemented as an alternative germanide S/D formation technique. A germanium p-MOSFET with Pt-germanide Schottky S/D formed by laser annealing was successfully demonstrated.