TCAD MODELLING AND CHARACTERIZATION OF DEFECTS IN ADVANCED NANOSCALE SEMICONDUCTOR DEVICES

Abstract

Semiconductor Failure Analysis (FA) has been crucial in the development of semiconductor process, yield enhancement and product development. Due to the device scaling and adoption of new technology such as FinFET, it has resulted in challenges in achieving good success rate in FA. However, due to the non-planar structure of FinFET and Gate-All-Around (GAA) devices, it is difficult to employ these techniques on these devices with good success rate. Therefore, a new method of defect library coupled with defect prediction technique is proposed. Due to the low occurrence of defects in actual devices, it is necessary to use a TCAD defect model to build up the defect library with different defect types. This work hence involves the introduction of defects into the TCAD transistor model and simulation of their electrical behavior. The electrical behavior is characterized based on signatures unique to the defect. Further investigation includes study of defect electrical behavior for complex circuit such as multiple-fins FinFET transistor and a 6T-SRAM bitcell. Lastly, the use of machine-learning for defect location prediction is also presented in this report, in which the random forest machine-learning classifier algorithm is implemented to classify and predict defect location within a single fin FinFET transistor.