Please use this identifier to cite or link to this item: https://doi.org/10.1109/NVMTS.2013.6851056
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dc.titleRobust Low-power Multi-terminal STT-MRAM
dc.contributor.authorFong, Xuanyao
dc.contributor.authorRoy, Kaushik
dc.date.accessioned2019-07-03T04:09:11Z
dc.date.available2019-07-03T04:09:11Z
dc.date.issued2013-01-01
dc.identifier.citationFong, Xuanyao, Roy, Kaushik (2013-01-01). Robust Low-power Multi-terminal STT-MRAM. 13th Non-Volatile Memory Technology Symposium (NVMTS). ScholarBank@NUS Repository. https://doi.org/10.1109/NVMTS.2013.6851056
dc.identifier.isbn9781479941100
dc.identifier.urihttps://scholarbank.nus.edu.sg/handle/10635/156217
dc.description.abstractBi-directional write current for writing '1' and '0', and shared read and write current paths severely limit the design space of spin-transfer torque MRAMs (STT-MRAM). Failure mitigation techniques proposed in the literature may be insufficient for realizing the full potential of STT-MRAMs at scaled MTJ dimensions due to asymmetries in MTJ characteristics and in access transistor drive-ability. This paper shows how STT-MRAM based on multi-terminal structures can overcome some of the above design constraints, leading to robust low-power STT-MRAM suitable for on-chip cache applications. © 2013 IEEE.
dc.publisherIEEE
dc.sourceElements
dc.subjectScience & Technology
dc.subjectTechnology
dc.subjectComputer Science, Hardware & Architecture
dc.subjectEngineering, Electrical & Electronic
dc.subjectComputer Science
dc.subjectEngineering
dc.typeConference Paper
dc.date.updated2019-07-03T03:50:04Z
dc.contributor.departmentDEPT OF ELECTRICAL & COMPUTER ENGG
dc.description.doi10.1109/NVMTS.2013.6851056
dc.description.sourcetitle13th Non-Volatile Memory Technology Symposium (NVMTS)
dc.published.statePublished
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