Please use this identifier to cite or link to this item:
https://doi.org/10.1109/NVMTS.2013.6851056
Title: | Robust Low-power Multi-terminal STT-MRAM | Authors: | Fong, Xuanyao Roy, Kaushik |
Keywords: | Science & Technology Technology Computer Science, Hardware & Architecture Engineering, Electrical & Electronic Computer Science Engineering |
Issue Date: | 1-Jan-2013 | Publisher: | IEEE | Citation: | Fong, Xuanyao, Roy, Kaushik (2013-01-01). Robust Low-power Multi-terminal STT-MRAM. 13th Non-Volatile Memory Technology Symposium (NVMTS). ScholarBank@NUS Repository. https://doi.org/10.1109/NVMTS.2013.6851056 | Abstract: | Bi-directional write current for writing '1' and '0', and shared read and write current paths severely limit the design space of spin-transfer torque MRAMs (STT-MRAM). Failure mitigation techniques proposed in the literature may be insufficient for realizing the full potential of STT-MRAMs at scaled MTJ dimensions due to asymmetries in MTJ characteristics and in access transistor drive-ability. This paper shows how STT-MRAM based on multi-terminal structures can overcome some of the above design constraints, leading to robust low-power STT-MRAM suitable for on-chip cache applications. © 2013 IEEE. | Source Title: | 13th Non-Volatile Memory Technology Symposium (NVMTS) | URI: | https://scholarbank.nus.edu.sg/handle/10635/156217 | ISBN: | 9781479941100 | DOI: | 10.1109/NVMTS.2013.6851056 |
Appears in Collections: | Staff Publications Elements |
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