Please use this identifier to cite or link to this item: https://doi.org/10.1109/LPE.2006.4271798
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dc.titleAnalysis of super cut-off transistors for ultralow power digital logic circuits
dc.contributor.authorRaychowdhury, Arijit
dc.contributor.authorFong, Xuanyao
dc.contributor.authorChen, Qikai
dc.contributor.authorRoy, Kaushik
dc.date.accessioned2019-07-03T03:53:36Z
dc.date.available2019-07-03T03:53:36Z
dc.date.issued2006-01-01
dc.identifier.citationRaychowdhury, Arijit, Fong, Xuanyao, Chen, Qikai, Roy, Kaushik (2006-01-01). Analysis of super cut-off transistors for ultralow power digital logic circuits. International Symposium on Low Power Electronics and Design : 2-7. ScholarBank@NUS Repository. https://doi.org/10.1109/LPE.2006.4271798
dc.identifier.isbn1-59593-462-6
dc.identifier.urihttps://scholarbank.nus.edu.sg/handle/10635/156201
dc.publisherASSOC COMPUTING MACHINERY
dc.sourceElements
dc.subjectScience & Technology
dc.subjectTechnology
dc.subjectComputer Science, Hardware & Architecture
dc.subjectEngineering, Electrical & Electronic
dc.subjectComputer Science
dc.subjectEngineering
dc.subjectcarbon nanotube FETs
dc.subjecttunneling transistors
dc.typeConference Paper
dc.date.updated2019-07-03T03:42:02Z
dc.contributor.departmentDEPT OF ELECTRICAL & COMPUTER ENGG
dc.description.doi10.1109/LPE.2006.4271798
dc.description.sourcetitleInternational Symposium on Low Power Electronics and Design
dc.description.page2-7
dc.published.statePublished
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