Please use this identifier to cite or link to this item: https://doi.org/10.1109/ASPDAC.2009.4796586
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dc.titleA Design Methodology and Device/Circuit/Architecture Compatible Simulation Framework for Low-Power Magnetic Quantum Cellular Automata Systems
dc.contributor.authorAugustine, Charles
dc.contributor.authorBehin-Aein, Behtash
dc.contributor.authorFong, Xuanyao
dc.contributor.authorRoy, Kaushik
dc.date.accessioned2019-07-03T03:50:16Z
dc.date.available2019-07-03T03:50:16Z
dc.date.issued2009-01-01
dc.identifier.citationAugustine, Charles, Behin-Aein, Behtash, Fong, Xuanyao, Roy, Kaushik (2009-01-01). A Design Methodology and Device/Circuit/Architecture Compatible Simulation Framework for Low-Power Magnetic Quantum Cellular Automata Systems. 14th Asia and South Pacific Design Automation Conference : 847-852. ScholarBank@NUS Repository. https://doi.org/10.1109/ASPDAC.2009.4796586
dc.identifier.isbn978-1-4244-2748-2
dc.identifier.issn2153-6961
dc.identifier.urihttps://scholarbank.nus.edu.sg/handle/10635/156198
dc.description.abstractCMOS device scaling is facing a daunting challenge with increased parameter variations and exponentially higher leakage current every new technology generation. Thus, researchers have started looking at alternative technologies. Magnetic Quantum Cellular Automata (MQCA) is such an alternative with switching energy close to thermal limits and scalability down to 5nm. In this paper, we present a circuit/architecture design methodology using MQCA. Novel clocking techniques and strategies are developed to improve computation robustness of MQCA systems. We also developed an integrated device/circuit/system compatible simulation framework to evaluate the functionality and the architecture of an MQCA based system and conducted a feasibility/comparison study to determine the effectiveness of MQCAs in digital electronics. Simulation results of an 8-bit MQCA-based Discrete Cosine Transform (DCT) with novel clocking and architecture show up to 290X and 46X improvement (at iso-delay and optimistic assumption) over 45nm CMOS in energy consumption and area, respectively. © 2009 IEEE.
dc.publisherIEEE
dc.sourceElements
dc.subjectScience & Technology
dc.subjectTechnology
dc.subjectComputer Science, Hardware & Architecture
dc.subjectEngineering, Electrical & Electronic
dc.subjectComputer Science
dc.subjectEngineering
dc.subjectNANOMAGNETS
dc.subjectFIELD
dc.subjectLOGIC
dc.typeConference Paper
dc.date.updated2019-07-03T03:37:53Z
dc.contributor.departmentDEPT OF ELECTRICAL & COMPUTER ENGG
dc.description.doi10.1109/ASPDAC.2009.4796586
dc.description.sourcetitle14th Asia and South Pacific Design Automation Conference
dc.description.page847-852
dc.published.statePublished
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