ENERGY AND AREA EFFICIENT MAGNETIC TUNNEL JUNCTION BASED NON-VOLATILE MEMORY AND LOGIC

Abstract

In the era of Internet-of-Things (IoT) and machine learning, ultra-low power and energy efficient computing become essential. Thus, emerging technologies and devices such as magnetic tunnel junctions (MTJs) have been developed to further reduce the various designs energy and silicon area consumptions. In particular, the non-volatility of such emerging technologies help eliminating the leakage current. Therefore, this thesis proposes three improved non-volatile memory cells and non-volatile flip-flops (NVFF). For non-volatile memory cells, spin-orbit torque magnetic random-access memory (SOT-MRAM) is targeted. This is mainly due to its various advantages such as high energy efficiency, performance, device reliability and unlimited endurance besides its non-volatility. The proposed designs focus on decreasing the overall consumed silicon area of the SOT-MRAM. Our proposed SOT-MRAM cells may achieve up to 90% smaller silicon area compared to the well-known static random-access memory (SRAM). They may also achieve 75% reduction in the silicon area compared to the conventional SOT-MRAM cell. Furthermore, various NVFF designs that rely on both spin transfer torque (STT) and SOT technologies are proposed. Our proposed NVFFs design offers the lowest area overhead compared to others, which requires only one overhead transistor. They also attain lower or similar energy and power consumptions.