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Title: Synthesis of multiprocessor architectures for multimedia applications
Keywords: MPSoC, MPEG2, Process Networks, Streaming, Network Calculus, Design Space Exploration
Issue Date: 6-Jun-2006
Citation: DINESH RAJENDRA KUNCHAMWAR (2006-06-06). Synthesis of multiprocessor architectures for multimedia applications. ScholarBank@NUS Repository.
Abstract: Streaming applications typically consist of a large number of tasks, each of which can be mapped onto a different processor on a Multi-processor System on Chip (MPSoC) platform. This gives rise to a large design space (whose size can be exponential in the number of tasks in the application). Previous work on design space exploration for this problem use evolutionary algorithms which do not guarantee optimality and are too time-consuming because of the need for full-system simulation. This problem has also been formulated as Integer Linear Programming problem assuming constant execution requirements. However high degree of burstiness in the arrival rate of streams and high variability in the execution demand of the data items, make those approaches adequate. In this work we present a depth-first design space exploration technique which breaks down the process of system simulation into many task level simulations. The results of the task level simulations are represented using Variability Characterization Curves (VCCs) which are based on theory of network calculus. We formulated an algorithm which explores the design space in a depth first manner and combines the VCCs of task mappings along the explored path using purely analytical methods. The algorithm avoids exhaustive searching of the design space by using certain timing conditions and upper bounds on the costs to prune some portions of design space. We take the multi-objective optimization approach for this problem and device a technique that is capable of finding a pareto optimal front. This allows the designer to make trade-offs among various design goals to quickly narrow down the choice of various architecture design parameters. We implemented our scheme and performed a case study based on the MPEG-2 decoder application. We demonstrated the usefulness of our multi-objective technique using two objectives: the silicon area required to realize the MPSoC system and power requirements of the system. For this case study, 76% of the design space was pruned due to the timing and upper bound conditions which translated into 74% saving in the running time of the algorithm.
Appears in Collections:Master's Theses (Open)

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