Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/154217
Title: YIELD ENGINEERING AND IMPROVEMENT ON SEMICONDUCTOR DEVICES
Authors: ANG SZE WEI KELVIN
Keywords: Yield Improvement
Yield Methodology
Issue Date: 2003
Citation: ANG SZE WEI KELVIN (2003). YIELD ENGINEERING AND IMPROVEMENT ON SEMICONDUCTOR DEVICES. ScholarBank@NUS Repository.
Abstract: In this project, total yield has been observed to stay in a range between 70% - 80%. The total yield never exceeds the 90% mark. Thus, the yield improvement methodology was carried out. Initial investigations by wafer map identified the main problem. Low edge yield had contributed largely to the overall non-yielding percentage. Subsequently, electrical testing correlation had been conducted to identify one of the root causes which are Inter Metal Oxide Thickness. Data from testers has indicated another probable cause which is Metal Shorting. Deeper analyses into the two root causes were done and their respective issues had been explored. Dielectric sloping profile, misalignment and metal under-etching are among the many issues. Yield improvement solutions that emerged from a variety of experiments are: 1) Improve via and metal printing at the wafer edge using optimized setting on lithography scanner: referred to as X-leveling Printing 2) Chemical Mechanical Planarization (CMP) using modified hardware inside the polishing tool: referred to as 52 mil CMP Template 3) Improve metal etch: referred to as 10s Metal Over-etch Experiments in the form of split plans were carried to verify the impact of the three solutions. Results from these three solutions proved to be promising in edge yield improvement. These solutions were then implemented on the production lots. As expected, the production lots shows significant improvement in yields.
URI: https://scholarbank.nus.edu.sg/handle/10635/154217
Appears in Collections:Master's Theses (Restricted)

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ANG SZE WEI KELVIN_Abstract.doc50.5 kBMicrosoft Word

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ANG SZE WEI KELVIN_ACKNOWLEDGEMENTS.doc36.5 kBMicrosoft Word

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ANG SZE WEI KELVIN_Appendix A.doc30.5 kBMicrosoft Word

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ANG SZE WEI KELVIN_Appendix A1(devices).doc1.36 MBMicrosoft Word

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ANG SZE WEI KELVIN_Appendix(A10).doc135.5 kBMicrosoft Word

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ANG SZE WEI KELVIN_CHAPTER 1(Introduction3).doc1.18 MBMicrosoft Word

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ANG SZE WEI KELVIN_CHAPTER 2(Yield intro2).doc61.5 kBMicrosoft Word

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ANG SZE WEI KELVIN_CHAPTER 3(yield method2).doc10.7 MBMicrosoft Word

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ANG SZE WEI KELVIN_CHAPTER 4(Yield edge).doc751 kBMicrosoft Word

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ANG SZE WEI KELVIN_CHAPTER 5(Yield Improve).doc67 kBMicrosoft Word

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ANG SZE WEI KELVIN_CHAPTER 6(Results).doc431.5 kBMicrosoft Word

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ANG SZE WEI KELVIN_CHAPTER 7(Con&Rec).doc74.5 kBMicrosoft Word

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ANG SZE WEI KELVIN_Cover Page.doc19 kBMicrosoft Word

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ANG SZE WEI KELVIN_LIST OF FIGURES.doc55.5 kBMicrosoft Word

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ANG SZE WEI KELVIN_LIST OF REFERENCES.doc62.5 kBMicrosoft Word

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ANG SZE WEI KELVIN_SUMMARY.DOC26 kBMicrosoft Word

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ANG SZE WEI KELVIN_TABLE OF CONTENTS.doc84.5 kBMicrosoft Word

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ANG SZE WEI KELVIN_Yield Engineering and Improvement on Semiconductor Devices.doc21 kBMicrosoft Word

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