DEVICE ELECTRICAL CHARACTERIZATION USING STATISTICAL ANALYSIS METHODS TO SETUP AN OPTIMAL TRIGGERING AND ANALYSIS SYSTEM

Abstract

In the semiconductor fabrication process, a bias current measurement, Idd, is often performed at Diesort testing. Some products exhibit Idd variations that can be linked to yield loss because of the bias current out of Diesort specification limits. However, the exact impact on the yield is difficult to be quantified, as there is a tolerance envelope only outside of which we may observe a hit in the yield. This project is meant to shed light on the Idd parameters and their boundary values that bring about an effect on the final yield by matching them with the Wafer Acceptance Test data matrix. The process of monitoring requires an effective triggering system that can alert engineers when a statistical fluctuation happens in the critical parameters that define yield “ be it yield, bin trends or the chamber effect. This project deals with explaining the design and execution of such a system as well.