FIN FET SIDE WALL FORMATION, CHARACTERIZATION AND RELATED SIMULATION

Abstract

As performance driven MOSFET scaling reaches in the sub-100 nm region, the conventional bulk CMOS device structure suffers from the severe short channel effect. In order to control such effects, a new material or device structures including the double-gate has been proposed. Fin FET, a vertical double-gate structure, appears to be a strong candidate. In Fin FET, as the gate dielectric formed on the sidewalls, the oxide properties depend upon surface roughness, orientation and oxide growth of the silicon sidewalls. To study the sidewalls oxide properties, a Fin (silicon pillar) MOS Capacitor test structure has been designed, fabricated and characterized. Lateral hard mask etching is carried out to achieve the better sidewall surface roughness and smaller dimensions from the 0.8 µm optical lithography. In order to verify the MOS fabrication process as well as characteristics, the Tsuprem4TM and MediciTM simulations are performed. These results can be useful for the device characteristics optimization on the 3-D device structures.