C-V MEASUREMENTS OF ULTRA THIN GATE MOSFETS (METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR)

Abstract

Accurate determination of device capacitance is critical for numerous first order data extraction including inversion thickness - an important parameter needed to be monitored for device control and development. However, as the oxide thickness is reduced and gate dielectrics comprised of stacks of novel materials are employed, C-V measurement and analysis are made more complex by the frequency-dependence of the measured capacitance. In this project, C-V characteristics of device test layouts of "pad" and "finger" structures with different substrate connections were studied. Also, the effect of deep n-well inclusion for elimination of chuck-related parasitics in gate capacitance measurement of n-MOSFETs was investigated. It is concluded that deep n-well inclusion has positive effects on C-V measurement of n-MOSFET devices. Sub-20Å gate oxide MOSFETs of "finger" structure give C-V curves of high accuracy. This finding offers a C-V measurement methodology with several advantages over conventional test structures and other C-V reconstruction methods such as real time measurement, high accuracy, ease of calibration, and simple post-data extraction.