DEVELOPMENT OF PLASMA ETCHING AND STRIPPING PROCESSES OF LOW-K DIELECTRICS FOR COPPER DAMASCENE METALLISATION

Abstract

With the continual shrinkage of device dimensions, the interconnect resistance-capacitance (RC) delay begins to govern the overall device delay. An effective method of reducing the RC delay is to replace the traditional silicon oxide with low-K dielectrics. This project evaluates the etching and stripping processes of a new chemical vapour deposition (CVD) low-K dielectric. Trial runs were first performed using different gas chemistries for opening bottom anti-reflective coating (BARC), etching and photoresist stripping. From the results of these preliminary experiments, a design of experiment (DOE) using CF₄/O₂/Ar gas chemistry was generated and performed to evaluate the etching process. Etch characteristics including selectivity, uniformity, microtrenching and critical dimensions (CD) loss were studied. Results of this designed experiment were then analysed to find an optimum etching process.