Alternative gate dielectrics and application in nanocrystal memory

Abstract

Nanocrystal memory has attracted much attention because it has better scalability than the conventional floating gate Flash memory. In this work, the performance of germanium (Ge) nanocrystal memory structures, employing high dielectric constant (high-k) materials to replace the tunnel oxide and capping oxide (control oxide) layers, was investigated. It was found that faster charging rate and better charge retention performance could be obtained with a high-k tunnel dielectric layer of equivalent oxide thickness (EOT) to that of silicon dioxide. Even at an EOT of 1.9 nm, the high-k layer is still physically thick enough to prevent Ge penetration into the substrate during high temperature annealing. If Ge penetration were to occur, Ge nanocrystals will not be able to form and the device will not show any charge storage effect. The replacement of the capping oxide layer with a high-k material of similar physical thickness as that of a silicon dioxide capping layer will result in better gate electric field coupling. The effect of gate electric field coupling on the conductance-voltage (G-V) characteristics of different trilayer nanocrystal memory structures was also investigated. It was found that the distinctive G-V characteristics due to nanocrystals could be separated and identified from the interface traps provided the memory structure has sufficiently high electric field coupling from the gate applied voltage. A method for calculating the density of nanocrystals based on the G V data was also discussed. Finally, investigation of trap energy levels in Ge nanocrystal memory structures and their effect on the device charging and discharging kinetics were also carried out by monitoring the transient drain current characteristics.