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https://scholarbank.nus.edu.sg/handle/10635/153875
DC Field | Value | |
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dc.title | Improving Latency for Electronic Trading Applications | |
dc.contributor.author | YING XIONG | |
dc.date.accessioned | 2019-05-09T04:10:06Z | |
dc.date.available | 2019-05-09T04:10:06Z | |
dc.date.issued | 2010 | |
dc.identifier.citation | YING XIONG (2010). Improving Latency for Electronic Trading Applications. ScholarBank@NUS Repository. | |
dc.identifier.uri | https://scholarbank.nus.edu.sg/handle/10635/153875 | |
dc.description.abstract | The latency problem is a popular topic, especially in the fast paced financial industry where low latency is one of the key factors for success. This thesis is based on the author’s work on reducing latencies in different workflows at Bank of America Merrill Lynch. The methodology is also applicable to other systems in general. A systematic look is given to identify the areas of latency within a set of Rates and Currencies based systems and solutions are proposed which can be practically applied and implemented without adverse impact to the functionality and operability. Different perspectives of a system are focused on: hardware, software, network, database and workflow. Hardware includes processors, network, storage, etc. Software includes appropriate code of programming, optimized way of programming which makes the code less reliant on particular compilers, and proper choice of languages and compilers. Workflow optimization requires thorough review of the whole workflow from start to end and is especially worth investigating for multi-processor scenarios. The pipelined workflow approach by Agrawal et al. can be used to optimize single port or multi-port workflows. It makes an assumption that the mapping relations between stages and processors are already given, and schedules the processors based on the mapping. The second method by Vydyanathan et al. has looser assumptions. It uses a directed acyclic graph to represent the workflow and can map stages/tasks to processors. It takes the better of the results from the three stage algorithm and the results generated by Kwok’s Static Scheduling Algorithms. The first method is simpler to adopt, easier to implement and can deal with single linear pipelined workflow perfectly; while the second method is more complicated, less time efficient and makes few pre-assumptions, and thus can be used for not only pipelined workflows, but also any other workflows with no restrictions | |
dc.source | SMA BATCHLOAD 20190422 | |
dc.subject | latency | |
dc.subject | performance | |
dc.subject | capacity | |
dc.subject | workflow | |
dc.subject | scheduling | |
dc.subject | mapping | |
dc.subject | DAG | |
dc.subject | robustness | |
dc.type | Thesis | |
dc.contributor.department | SINGAPORE-MIT ALLIANCE | |
dc.contributor.supervisor | KHOO BOO CHEONG | |
dc.contributor.supervisor | MICHAEL LOWE | |
dc.description.degree | Master's | |
dc.description.degreeconferred | MASTER OF SCIENCE IN COMPUTATIONAL ENGINEERING | |
dc.description.other | Dissertation Supervisors: 1. Michael John Lowe, Assistant Vice President, Bank of America Merrill Lynch 2. Prof Khoo Boo Cheong, National University of Singapore | |
Appears in Collections: | Master's Theses (Restricted) |
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Ying Xiong_Improving Latency for Electronic Trading Applications - XIONG Ying.pdf | 460.89 kB | Adobe PDF | RESTRICTED | None | Log In |
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