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|Title:||Design of CMOS receivers and building blocks for ultra- wideband radio||Authors:||TONG YAN||Keywords:||ultra-wideband, receiver, DC-offset, multiplier, variable gain amplifier, integrator.||Issue Date:||14-Apr-2006||Citation:||TONG YAN (2006-04-14). Design of CMOS receivers and building blocks for ultra- wideband radio. ScholarBank@NUS Repository.||Abstract:||In this thesis, receiver systems and CMOS integrated circuits design for Ultra-Wideband (UWB) communication are proposed.Several building blocks for the receivers are designed in a 0.18-i?-m CMOS technology. Cross-coupled transistors with source followers are used to implement the multiplier. Inductor peaking technique is employed to enhance multiplier bandwidth with more than 7 GHz bandwidth. A continuous-time negative feedback loop is employed in the VGA to suppress DC-offset by 15 dB while obtaining 45 dB dynamic range. The integrator employs structure to obtain a unit gain frequency of around 1 GHz and low -3 dB bandwidth of less than 1MHz. Two UWB receiver architectures are proposed and implemented using the proposed building blocks. The coherent receiver achieves simulated transmission rate of 100 MHz and sensitivity of -80 MHz, and the non-coherent receiver achieves measured transmission rate of 50 MHz and sensitivity of -65 dBm.||URI:||http://scholarbank.nus.edu.sg/handle/10635/15285|
|Appears in Collections:||Master's Theses (Open)|
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