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Title: Simulation of board level drop test for wafer level packages
Authors: GU JIE
Keywords: electronic package, drop test, modeling and simulation
Issue Date: 25-Dec-2005
Citation: GU JIE (2005-12-25). Simulation of board level drop test for wafer level packages. ScholarBank@NUS Repository.
Abstract: Reliability of IC packages during drop impact is critical for portable electronic products. Normally, portable products are designed to withstand a few accidental drops without resulting in major mechanical failure. In this study, the ABAQUS/EXPLICIT finite element software is used to perform the dynamic drop impact simulation. Currently, to satisfy the demands of increase in I/O (input/output) and decrease in package size, the number of interconnects in the package has also increased dramatically. As a result, this poses a great challenge to performing simulation as it is too time consuming and takes too much memory to model the huge numbers of interconnects. This research work presents Equivalent Layer models for performing simulation of the mechanical response of interconnects under drop impact. By using these new equivalent models, two interconnect structures a?? SSC (Stretched Solder Column) and BON (Bed of Nail) under drop impact in wafer level packages are studied. It is shown that by using these new equivalent models, the model size and computational processing time can be greatly reduced, while maintaining the high accuracy of the results.
Appears in Collections:Master's Theses (Open)

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