Microarchitecture modeling for timing analysis of embedded software

Abstract

A fundamental problem for real-time computing is to know the Worst Case Execution Time (WCET) of the tasks. To obtain safe and tight WCET estimates, it is essential to take into account the effects of hardware features on instruction timing. In this thesis, we study advanced hardware features commonly found in high-performance processors to model their timing effects on the execution of programs. The modeled features modeled include out-of-order pipelines, dynamic branch predictions, which have not been modeled effectively by other researchers. A framework for modeling the combination of the three most important micro-architectural features ( pipelining, instruction caching, and branch prediction) is proposed. This thesis significantly extends the state-of-the-art, and the novel techniques provide a good basis for applying high-performance processors in real-time embedded applications., and the novel techniques provide a good basis for applying high-performance processors in real-time embedded applications.