Please use this identifier to cite or link to this item:
Title: Design of a fully digital multi-level decision feedback equalization chip
Authors: XIE JIANG
Keywords: MDFE, Decision Feedback, Equalizer, Read Channel, ASIC
Issue Date: 15-Mar-2005
Citation: XIE JIANG (2005-03-15). Design of a fully digital multi-level decision feedback equalization chip. ScholarBank@NUS Repository.
Abstract: The design and implementation of a Multi-level Decision Feedback Equalization (MDFE) chip for magnetic recoding channel application is described. The architecture of the single-chip MDFE incorporates an 8-tap feed-forward equalizer and a 10-tap feedback equalizer. The feed-forward section (FFE) is a linear transposed filter that removes the linear precursor intersymbol interference (ISI) by a sufficient length to delay the channel response to make it causal. The feedback section (FBE) uses the decision feedback technique to eliminate non-linear postcursor ISI by a look-up table based structure with the past decisions being the addresses. Based on a 0.35-A?m CMOS technology, the final design shows that at post-layout level the MDFE chip can operate at a clock rate of 170MHz in TYPICAL condition, 230MHz in BEST case, and 125MHz in WORST case. The chip, which is composed of 73,386 gates and 54 I/O pads, has the chip area of 4.4mm2, and consumes dynamic power of 143.03mW under a 3.3-V supply.
Appears in Collections:Master's Theses (Open)

Show full item record
Files in This Item:
File Description SizeFormatAccess SettingsVersion 
E_THESIS_XJ_2005.pdf3.12 MBAdobe PDF



Page view(s)

checked on May 22, 2019


checked on May 22, 2019

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.