Stress-induced leakage current in dual-gate CMOSFETS with thin nitrided gate oxides

Abstract

Beginning with a brief review of the literature about stress-induced leakage current (SILC), a study of the SILC in the dual-gate CMOSFET with 2.2 nm nitrided gate oxide has been presented, from the observation of the evolution of hole and electron current components. In the p+/pMOSFET, the hole component of the SILC dominates over the electron component, and such dominance is enhanced continuously during stress. A physical model, featuring two separate energy distributions of oxide traps and favoring hole tunneling in the p+/pMOSFET, is proposed to explain the observed evolution of hole current and electron current components. Oxide trap localization near the substrate valence band is probably responsible for the dominance of hole current. Such a localized trap distribution could be generated by hole injection into the gate oxide. The proposed physical model is consistent with the established TAT framework for SILC. In the n+/nMOSFET, SILC is found to be dominated by the conduction-band electron tunneling, which is attributed to the trap-assisted tunneling (TAT) mechanism facilitated by a heavily one-sided stress-induced trap distribution, localized near the substrate conduction band edge. Degradation of the ultrathin gate oxide process can be well visualized by the generation and increase of SILC. Before oxide breakdown happens, both p+/pMOS and n+/nMOS demonstrated the partial recovery of degradation after the withdrawal of stress voltage but before the oxide breakdown. A solid correlation exists between degradation rate of the gate oxide and charge injection. The sharp decrease of SILC generation probability at high charge injection indicates that neutral oxide trap generation tends to saturate at high stress level.