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|Title:||Titanium self-aligned silicide process fabrication issues for deep sub-micron CMOS devices||Authors:||Lahiri, S.K.
|Issue Date:||1998||Citation:||Lahiri, S.K., Lim, C.W., Chan, L. (1998). Titanium self-aligned silicide process fabrication issues for deep sub-micron CMOS devices. Proceedings of SPIE - The International Society for Optical Engineering 3316 (2) : 957-966. ScholarBank@NUS Repository.||Abstract:||As miniaturization of microelectronic devices continues into the deep sub-micron range, a number of material properties become critically important for device performance and reliability. These include gate-to-source/drain leakage, junction leakage, series and contact resistances at the poly-Si gate and source/drain region. Self-aligned silicide (SALICIDE) process using titanium silicide is a attractive process for the fabrication of deep sub-micron high performance CMOS devices because it can satisfy some of the critical material requirements. Consequently, a great deal of work is in progress worldwide to develop an appropriate SALICIDE process for deep sub-micron devices in order to improve performance and minimize leakages. In this article important issues regarding the titanium self-aligned silicide process, as well as the direction of the current research in modifying the process, for the fabrication of deep sub-micron CMOS devices will be presented.||Source Title:||Proceedings of SPIE - The International Society for Optical Engineering||URI:||http://scholarbank.nus.edu.sg/handle/10635/134142||ISSN:||0277786X|
|Appears in Collections:||Staff Publications|
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