Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/13131
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dc.titleStudy on advanced gate stack using high-k dielectric and metal electrode
dc.contributor.authorHWANG WAN SIK
dc.date.accessioned2010-04-08T10:30:18Z
dc.date.available2010-04-08T10:30:18Z
dc.date.issued2008-06-02
dc.identifier.citationHWANG WAN SIK (2008-06-02). Study on advanced gate stack using high-k dielectric and metal electrode. ScholarBank@NUS Repository.
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/13131
dc.description.abstractMetal/High-K gate stack will replace conventional poly-Si gate stack for continuous scaling of CMOS technology. In this thesis, several challenges on formation of Metal/High-K gate stacks have been discussed. Firstly, anisotropy gate stack of TaN, TiN, and HfN with high selectivity over under-laying high-k was formed. The etching and high selectivity mechanisms were explored in detail. Secondly, retard of etching rates of TaN, TiN, and HfN under the SiO2/Si3N4 hard was observed. Thirdly, ion assisted wet removal of (HfO2)x(SiON)1-x high dielectric constant materials and its effect on electrical properties were investigated. Lastly, Hafnium carbide (HfCx) is investigated as a novel metal gate electrode with good thermal stability for the first time.
dc.language.isoen
dc.subjectMetal electrode, high-k dielectrics, gate stacks, plasma etching, TaN, HfO2
dc.typeThesis
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.contributor.supervisorCHO BYUNG-JIN
dc.contributor.supervisorCHAN SIU HUNG, DANIEL
dc.contributor.supervisorYOO WON JONG
dc.description.degreePh.D
dc.description.degreeconferredDOCTOR OF PHILOSOPHY
dc.identifier.isiutNOT_IN_WOS
Appears in Collections:Ph.D Theses (Open)

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