Please use this identifier to cite or link to this item: https://doi.org/10.1109/TVLSI.2013.2267754
DC FieldValue
dc.titleSTT-RAM cache hierarchy with multiretention MTJ designs
dc.contributor.authorSun, Z.
dc.contributor.authorBi, X.
dc.contributor.authorLi, H.
dc.contributor.authorWong, W.-F.
dc.contributor.authorZhu, X.
dc.date.accessioned2016-06-02T09:25:19Z
dc.date.available2016-06-02T09:25:19Z
dc.date.issued2014
dc.identifier.citationSun, Z., Bi, X., Li, H., Wong, W.-F., Zhu, X. (2014). STT-RAM cache hierarchy with multiretention MTJ designs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (6) : 1281-1293. ScholarBank@NUS Repository. https://doi.org/10.1109/TVLSI.2013.2267754
dc.identifier.issn10638210
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/124980
dc.description.abstractSpin-transfer torque random access memory (STT-RAM) is the most promising candidate to be universal memory due to its good scalability, zero standby power, and radiation hardness. Having a cell area only 1/9 to 1/3 that of SRAM, allows for a much larger cache with the same die footprint. Such reduction of cell size can significantly shrink the cache array size, leading to significant improvement of overall system performance and power consumption, especially in this multicore era where locality is crucial. However, deploying STT-RAM technology in L1 caches is challenging because write operations on STT-RAM are slow and power-consuming. In this paper, we propose a range of cache hierarchy designs implemented entirely using STT-RAM that deliver optimal power saving and performance. In particular, our designs use STT-RAM cells with various data retention times and write performances, made possible by novel magnetic tunneling junction designs. For L1 caches where speed is of utmost importance, we propose a scheme that uses fast STT-RAM cells with reduced data retention time coupled with a dynamic refresh scheme. In the dynamic refresh scheme, another emerging technology, memristor, is used as the counter to monitor the data retention of the low-retention STT-RAM, achieving a higher array area efficiency than an SRAM-based counter. For lower level caches with relatively larger cache capacities, we propose a design that has partitions of different retention characteristics, and a data migration scheme that moves data between these partitions. The experiments show that on the average, our proposed multiretention level STT-RAM cache reduces total energy by as much as 30%-74.2% compared to previous single retention level STT-RAM caches, while improving instruction per cycle performance for both two-level and three-level cache hierarchies. © 2013 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/TVLSI.2013.2267754
dc.sourceScopus
dc.subjectCache hierarchy
dc.subjectmagnetic tunnel junction (MTJ)
dc.subjectretention time
dc.subjectspin-transfer torque random access memory (STT-RAM)
dc.subjectspintronic memristor
dc.subjectswitching current.
dc.typeArticle
dc.contributor.departmentCOMPUTER SCIENCE
dc.description.doi10.1109/TVLSI.2013.2267754
dc.description.sourcetitleIEEE Transactions on Very Large Scale Integration (VLSI) Systems
dc.description.volume22
dc.description.issue6
dc.description.page1281-1293
dc.description.codenIEVSE
dc.identifier.isiut000337167600008
Appears in Collections:Staff Publications

Show simple item record
Files in This Item:
There are no files associated with this item.

SCOPUSTM   
Citations

33
checked on May 17, 2022

WEB OF SCIENCETM
Citations

30
checked on May 17, 2022

Page view(s)

125
checked on May 12, 2022

Google ScholarTM

Check

Altmetric


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.