Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/121951
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dc.titleNOVEL III-V DEVICE ARCHITECTURES FOR APPLICATION IN ADVANCE CMOS LOGIC AND BEYOND
dc.contributor.authorGOH KIAN HUI
dc.date.accessioned2015-12-31T18:01:13Z
dc.date.available2015-12-31T18:01:13Z
dc.date.issued2015-07-29
dc.identifier.citationGOH KIAN HUI (2015-07-29). NOVEL III-V DEVICE ARCHITECTURES FOR APPLICATION IN ADVANCE CMOS LOGIC AND BEYOND. ScholarBank@NUS Repository.
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/121951
dc.description.abstractIII-V MOSFETs are one of the most attractive devices due to their extremely high electron mobility. However, new processes associated with III-V substrates must be simplified, and costs of integration on Si substrate should be reduced. First, ultra-thin-body (UTB) (1 nm-thick) In0.53Ga0.47As channel junctionless n-FET with raised S/D structure and shortest reported gate length (LG) of 6 nm was realized for III-V MOSFETs. Next, process for heteroepitaxial growth of high-quality InxGa1-xAs on Ge fin was developed. A physical modeling to describe the GaAs facets with different Ge fin orientation is proposed and verified experimentally. Finally, to further improve device SCEs, a novel vertically stacked nanowire (NW) CMOS (InAs n-FET and GaSb p-FET) on Si platform was demonstrated using extremely thin buffer layer (sub-120 nm) technology. Our NW devices achieved the best reported ION/IOFF ratio and swing for III-V CMOS integrated on silicon substrate.
dc.language.isoen
dc.subjectBand-Engineered, GaAs on Ge Growth, Vertically Stacked Nanowire, More than Moore, III-V on Si, novel device architecture
dc.typeThesis
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.contributor.supervisorYEO YEE CHIA
dc.description.degreePh.D
dc.description.degreeconferredDOCTOR OF PHILOSOPHY
dc.identifier.isiutNOT_IN_WOS
Appears in Collections:Ph.D Theses (Open)

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